کتابخانه

Features

• Discusses how to structure applications to take advantage of large multi/manycore massively parallel systems
• Discusses architectural features of the latest Intel Knight’s Landing (KNL) and Xeon multicore systems
• Covers how applications can take advantage of the architecture with vectorization and cache optimization
• Shows real world examples run on KNL and Xeon systems

Summary

"Ask not what your compiler can do for you, ask what you can do for your compiler."
--John Levesque, Director of Cray’s Supercomputing Centers of Excellence

The next decade of computationally intense computing lies with more powerful multi/manycore nodes where processors share a large memory space. These nodes will be the building block for systems that range from a single node workstation up to systems approaching the exaflop regime. The node itself will consist of 10’s to 100’s of MIMD (multiple instruction, multiple data) processing units with SIMD (single instruction, multiple data) parallel instructions. Since a standard, affordable memory architecture will not be able to supply the bandwidth required by these cores, new memory organizations will be introduced. These new node architectures will represent a significant challenge to application developers.

Programming for Hybrid Multi/Manycore MPP Systems attempts to briefly describe the current state-of-the-art in programming these systems, and proposes an approach for developing a performance-portable application that can effectively utilize all of these systems from a single application. The book starts with a strategy for optimizing an application for multi/manycore architectures. It then looks at the three typical architectures, covering their advantages and disadvantages.

The next section of the book explores the other important component of the target—the compiler. The compiler will ultimately convert the input language to executable code on the target, and the book explores how to make the compiler do what we want. The book then talks about gathering runtime statistics from running the application on the important problem sets previously discussed.

How best to utilize available memory bandwidth and virtualization is covered next, along with hybridization of a program. The last part of the book includes several major applications, and examines future hardware advancements and how the application developer may prepare for those advancements.

Table of Contents

Introduction
Introduction
Chapter Overviews

Determining an Exaflop Strategy
Foreword By John Levesque
Introduction
Looking At The Application
Degree Of Hybridization Required
Decomposition And I/O
Parallel And Vector Lengths
Productivity And Performance Portability
Conclusion

Target Hybrid Multi/Many Core System
Foreword By John Levesque
Understanding The Architecture
Cache Architectures
Memory Hierarchy
Knl Clustering Modes
Knl Mcdram Modes
Importance Of Vectorization
Alignment For Vectorization

How Compilers Optimize Programs
Foreword By John Levesque
Introduction
Memory Allocation
Memory Alignment
Comment-Line Directive
Interprocedural Analysis
Compiler Switches
Fortran 2003 And Inefficiencies
Compiler Scalar Optimizations

Gathering Runtime Statistics for Optimizing
Foreword By John Levesque
Introduction
What’s Important To Profile
Conclusion

Utilization of Available Memory Bandwidth
Foreword By John Levesque
Introduction
Importance Of Cache Optimization
Variable Analysis In Multiple Loops
Optimizing For The Cache Hierarchy
Combining Multiple Loops
Conclusion

Vectorization
Foreword By John Levesque
Introduction
Vectorization Inhibitors
Vectorization Rejection From Inefficiencies
Striding Versus Contiguous Accessing
Wrap-Around Scalar
Loops Saving Maxima And Minima
Multi-Nested Loop Structures
There’s Matmul And Then There’s Matmul
Decision Processes In Loops
Handling Function Calls Within Loops
Rank Expansion
Outer Loop Vectorization

Hybridization of an Application
Foreword By John Levesque
Introduction
The Node’s Numa Architecture
First Touch In The Himeno Benchmark
Identifying Which Loops To Thread
Spmd Openmp

Porting Entire Applications
Foreword By John Levesque
Introduction
Spec Openmp Benchmarks
Nasa Parallel Benchmark (Npb) - Bt
Refactoring Vh-1
Refactoring Leslie3d
Refactoring S3d – 2016 Production Version
Performance Portable – S3d On Titan

Future Hardware Advancements
Introduction
Future X86 Cpus
Future Arm Cpus
Future Memory Technologies
Future Hardware Conclusions

Appendices
Supercomputer Cache Architectures
The Translation Look-Aside Buffer
Command Line Options / Compiler Directives
Previously Used Optimizations
I/O Optimization
Terminology
12-Step Process